1. Field
Example embodiments relate generally to semiconductor integrated circuits and more particularly to a repair control circuit and a semiconductor memory device including the repair control circuit for replacing fail memory cells with redundancy memory cells in the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices include a plurality of memory cells that are arranged in a matrix form of a plurality of rows and a plurality of columns. The rows may correspond to wordlines to which respective row addresses are assigned and the columns may correspond to bitlines to which respective column addresses are assigned. The semiconductor memory devices may include normal memory cells and redundancy memory cells for replacing fail memory cells among the normal memory cells. In the conventional memory device, a row repair operation may be performed to replace one wordline with one redundancy wordline or a column repair operation may be performed to replace one bitline with one redundancy bitline.
As the integration density of the semiconductor memory device is increased, single-bit fail rate is increased. When the single-bit fail is dominant, the row-by-row repair and the column-by-column repair are inefficient because repair resources may be exhausted excessively and thus the integration density may be degraded. In case of implementing the bit-by-bit repair, the size or the occupation area of the peripheral circuitry is increased significantly to control the bit-by-bit repair operation.